In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called "metalization", and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the "damascene" technique starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as "barrier layer" herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or "seed", for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the "dual damascene" technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that adhesion/barrier layers are required. Materials such as tantalum (Ta), titanium (Ti), and tungsten (W), their alloys, their nitrides, or combinations thereof are used as adhesion/barrier materials for copper. The adhesion/barrier layers server several different roles. First, they promote greater adhesion of the copper to the oxide layer. Second, they prevent diffusion of copper into the dielectric layer. And, third, they improve the resistance of copper to electromigration, which is the movement of copper atoms under the influence of current flow, which can cause voids in the copper.
The adhesion/barrier layer improves the resistance to electromigration in two areas. First, along the length of a conductive channel in the direction of current flow where the adhesion/barrier layer will be on three sides of the copper and the good interface reduces copper surface electromigration. And, second, in the contact area of a via with the conductive channel where the current density is higher than in the conductive channel itself.
A problem, associated with the interface between the adhesion/barrier layer of the via and the copper layer in the conductive channel below the via, is the difficulty bonding the two layers. For example, to provide the excellent bonding of the two layers by intermixing, the two layers must be annealed, or heated above about 400.degree. C. Unfortunately, copper tends to clump, or agglomerate at temperatures above 150.degree. C. which means that the optimal bonding temperatures can not be used.
The copper seed layers for copper interconnect in a damascene process are typically deposited by physical vapor deposition (PVD) or derivatives of PVD techniques on top of the adhesion/barrier materials. The preferred method of deposition is by low temperature physical vapor deposition, at temperatures below 100.degree. C. or even 50.degree. C., specifically because of the agglomeration problem.
Another problem, associated with the interface between the adhesion/barrier layer of the via and the copper layer, is contamination between the two layers. If there were any contamination, this would lead to high contact resistance. Again high temperature intermixing would assure a good interface and result in lower contact resistance.
A solution, which would permit the formation of an intermixed layer between the via and its contacted channel has been long sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and thinner channels and narrower vias, it is becoming more pressing that a solution is found.